Diode bridge

Posted on by Ed Hare PhD

 

SEM Lab, Inc. performed failure analysis on a diode bridge.  Electrical tests results suggested that one of four internal diodes had short circuited.

 

The module was chemically decapsulated and the shorted die was isolated for SEM/EDS analysis. This is a BSE SEM image of the shorted die.

 

The suspected short site was located near a corner of the die.

 

An elemental map confirms that the suspected short is a silicon melt pipe.

 

Higher magnification images of the site also confirmed it is the breakdown site.

 

The size of the breakdown site is related to the melt-thru current [1], which in this case is estimated as ~14.3 amperes.  The location of the melt through suggests that the breakdown was caused by a high voltage transient.

[1] J. T. May, “Limiting Phenomena in Power Transistors and the Interpretation of EOS Damage”, in Microelectronics Failure Analysis Desk Reference, 3rd Edition, ASM International Press, 1993, pp. 321-328.

 

 

BGA Solder Joint Simulation

Posted on by Ed Hare PhD

 

 

SEM Lab, Inc. created a video (link below) to illustrate simulation of BGA solder joints during the reflow solder process.  This approach allows us to determine at what height the solder joint becomes unstable and separates into two droplets during reflow.  This simulation tool will be useful for identifying the BGA warpage value that would be expected to cause defects such as head-in-pillow.

 

Modeling BGA Solder Joints

QFN Failures

Posted on by Ed Hare PhD

QFN failures are increasingly important as more devices are offered in this package style, sometimes exclusively. There are some notable manufacturing issues related to assembly processes for QFNs, and this post discusses two of the more common ones that cause failures.

Trapped conductive residue under the device

The capillary gap under assembled QFNs is typically very small and difficult to clean, so solder flux residue and moisture lead to corrosion and electrical leakage causing what initially looks like a device failure. The example below shows this type of condition and resulted in failure.

Conductive residue and corrosion product trapped under QFN device.

Another example shows several QFN signals bridged by conductive residue.

Conductive residue bridging several signals on the assembled QFN.

CCE mismatch induced warpage and subsequent failure of solder joints

The QFN package typically contains a relatively large volume fraction of silicon relative to other package styles, which creates a significant CTE mismatch between the QFN and the board. In addition, the solder joint height is minimal resulting in increased stiffness of the solder joints. These factors can lead to substantial residual stress in the solder joints. Any additional mechanical stress due to depaneling or ICT probes can overload the solder joints resulting in fractures. The example below shows a fractured joint that popped up indicating there was residual elastic strain in the QFN and PWB after assembly.

Fracture QFN solder joint.
Higher magnification view of QFN solder joint fracture.

The examples of manufacturing issues related to assembly processes for QFNs discussed above suggest a need for rigorous process validation for both solder reflow and cleaning processes.

PWB Quality Problems

Posted on by Ed Hare PhD

Quality problems identified during failure analysis performed by SEM Lab, Inc. over the past couple of decades.

 

Bad HASL finish

Example 1

This is an example of bad HASL finish, likely due to inappropriate air knife pressure. The problem caused inadequate solder coverage of the component mounting pads, which resulted in exposed Cu-Sn IMC and caused a severe solderability problem during assembly of the PWAs.

Example 2

This example shows delamination of an internal layer. The delamination likely occurred as a result of a contaminant trapped at the interface between the B-stage and the copper-clad laminate during PWB lay-up.

Example 3

This example shows the condition referred to as resin recession, where resin recedes from the copper barrel after cooling from a thermal excursion.

Example 4

This is an example of poor drilled hole quality and thin (< 1-mil) copper plating of the hole walls.

Example 5

This is an example of a very high aspect ratio PTH-via on a high layer count board. The quality is very good considering the difficulty of fabricating high aspect ratio PTH-vias.

Example 6

This example shows poor drilled hole quality and resulting laminate damage including a substantial crack with copper plating extending well past the outside diameter of the PTH.

Example 7

This example shows gross damage after a conductive anodic filament shorted adjacent signals, +12V and GND at a through-hole connector.

Example 8

These are neighboring holes for the previous example that had not been damaged, which showed poor drilled hole quality, laminate damage, and copper plating extending well across the isolation space between PTHs.

Example 9

This is an example of inner layer separation from the PTH wall, which is most like due to resin smear and inadequate de-smearing prior to copper plating. This could have passed electrical testing as there is enough connection that it might not have been detected.

Example 10

This is another example of inner layer separation, which was likely exacerbated by a thermal excursion.

Example 11

This example shows a PTH-via with thin plating between two Vias with nominal plating thickness. There were plating nodules near the top and bottom of the hole that likely restricted access of the plating solution to the central region of the hole.

Example 12

This is a BGA assembly where the PTH-via on the right corroded open, which was due to poor via-fill allowing corrosive solder flux to become trapped in the hole.

 

Example 13

This PWB is an LED substrate with an over-molded body. The PTH copper shows and example of “skip plating” where no copper deposited on the hole wall. There is also thin plating on the opposite side. Together these resulted in an open circuit condition.

 

Example 14

This is an example of inadequate copper plating thickness in a PTH.

 

Example 15

This examples shows a circumferential barrel crack in the center of the PTH, which is likely due to a combination of excessive Z-axis expansion and perhaps poor copper ductility.

 

 

Example 16

This is an optical image of a micro-sectioned PWB using dark field imaging. The reflections of groups of glass fibers intersecting with the hole is an indication of laminate damage due to drilling, which can reduce CAF resistance.

 

 

Example 17

This is an example of a copper plating nodule on the ID of a PTH.

 

 

Example 18

This image shows delamination of epoxy resin from fiber bundles as well as resin starvation. It is likely that the resin starvation condition caused excessive moisture entrapment and subsequent popcorn damage when the moisture vaporized at elevated temperature (e.g. lamination or solder reflow).

 

 

Al Bond Pad with Ti-W Barrier

Posted on by Ed Hare PhD

 
SEM Lab, Inc. recently announced a new capability for measurement of thin film layer thickness using EDS data. This post shows an example where the aluminum bond pad thickness and the underlying Ti-W barrier metal layer thickness are measured simultaneously on a silicon IC device. Fig. A shows the EDS spectra of three bond pads on the device. Fig. B shows the layer thickness values for two different devices (A & B) at three different bond pads (1, 2, & 3).

Fig. A – EDS spectra of three bond pads on a device die.

Fig. B – Layer thickness values for two different devices (A & B) at three different bond pads (1, 2, & 3).

The ability to measure the aluminum bond pad thickness and the underlying Ti-W barrier metal layer thickness simultaneously makes this a very efficient method for characterizing IC devices.

Thin Film Thickness Measurements

Posted on by Ed Hare PhD

Thin Film Thickness Measurements Using EDS

 

SEM Lab, Inc. has developed a method for measuring thickness of thin film deposits on various substrates, including multiple layers of different materials, using EDS data.  The method is extremely efficient and is therefore a cost effect alternative to conventional and FIB microsection techniques (approximately half the cost).

One application for this method is measurement of aluminum deposits on silicon die, particularly wire bond pads. The example below (Fig. A) shows a BSE SEM image and raster scan EDS spectrum of an aluminum bond pad on silicon, and the calculated thickness of the aluminum layer.

A second example (Fig. B) is gold plating thickness over nickel or nickel-phosphorus alloy.  The thickness of the gold layer can be determined for electroless-nickel immersion-gold (ENIG) PWB finishes and thin electro-plated gold (< 15 microns) on boards or component leads.

There are numerous other applications for this measurement method, which has significant advantages over conventional direct measurements on cross-sections including,

  • Measurement requires only one EDS spectrum versus multiple direct measurements from cross-sections to achieve a meaningful average
  • Non-destructive to the location being examined
  • Simultaneous acquisition of image to document surface morphology
  • Approximately half the cost of conventional and FIB microsection techniques

In summary, SEM Lab, Inc. can provide thickness measurements of thin film deposits on various substrates, including multiple layers of different materials, using EDS data for approximately half the cost of conventional and FIB microsection techniques.  Please contact us to discuss your specific requirements for measurements of thin film deposit thickness.

BSE SEM image and raster scan EDS spectrum of aluminum bond pad on silicon.

Fig A – BSE SEM image and raster scan EDS spectrum of aluminum bond pad on silicon.

 

 

Gold over nickel-phosphorus alloy on flex connector contact fingers

Fig B – Gold over nickel-phosphorus alloy on flex connector contact fingers.

 

EOS Damaged Op Amp

Posted on by Ed Hare PhD

EOS damage on this chemically decapsulated operational amplifier was more subtle than most cases that we have analyzed. This suggests that the stress condition was likely just above the maximum operating conditions for the device. In this case the damage was associated with an output pin likely overloaded by another device.

Other examples of EOS damage can be found here …

Example 1  Example 2

BGA Assembly Verification

Posted on by Ed Hare PhD

 

BGA Assembly Verification

SEM Lab, Inc. provides a comprehensive approach to BGA assembly validation using microsection and SEM analysis.  The results can be used to optimize assembly processes early in the product development cycle and help to prevent failure during production. [see presentation]

BGA warpage - How much is too much?
Calculating warpage based on measurements from BGA microsections.