Quality problems identified during failure analysis performed by SEM Lab, Inc. over the past couple of decades.
Example 1
This is an example of bad HASL finish, likely due to inappropriate air knife pressure. The problem caused inadequate solder coverage of the component mounting pads, which resulted in exposed Cu-Sn IMC and caused a severe solderability problem during assembly of the PWAs.
Example 2
This example shows delamination of an internal layer. The delamination likely occurred as a result of a contaminant trapped at the interface between the B-stage and the copper-clad laminate during PWB lay-up.
Example 3
This example shows the condition referred to as resin recession, where resin recedes from the copper barrel after cooling from a thermal excursion.
Example 4
This is an example of poor drilled hole quality and thin (< 1-mil) copper plating of the hole walls.
Example 5
This is an example of a very high aspect ratio PTH-via on a high layer count board. The quality is very good considering the difficulty of fabricating high aspect ratio PTH-vias.
Example 6
This example shows poor drilled hole quality and resulting laminate damage including a substantial crack with copper plating extending well past the outside diameter of the PTH.
Example 7
This example shows gross damage after a conductive anodic filament shorted adjacent signals, +12V and GND at a through-hole connector.
Example 8
These are neighboring holes for the previous example that had not been damaged, which showed poor drilled hole quality, laminate damage, and copper plating extending well across the isolation space between PTHs.
Example 9
This is an example of inner layer separation from the PTH wall, which is most like due to resin smear and inadequate de-smearing prior to copper plating. This could have passed electrical testing as there is enough connection that it might not have been detected.
Example 10
This is another example of inner layer separation, which was likely exacerbated by a thermal excursion.
Example 11
This example shows a PTH-via with thin plating between two Vias with nominal plating thickness. There were plating nodules near the top and bottom of the hole that likely restricted access of the plating solution to the central region of the hole.
Example 12
This is a BGA assembly where the PTH-via on the right corroded open, which was due to poor via-fill allowing corrosive solder flux to become trapped in the hole.
Example 13
This PWB is an LED substrate with an over-molded body. The PTH copper shows and example of “skip plating” where no copper deposited on the hole wall. There is also thin plating on the opposite side. Together these resulted in an open circuit condition.
Example 14
This is an example of inadequate copper plating thickness in a PTH.
Example 15
This examples shows a circumferential barrel crack in the center of the PTH, which is likely due to a combination of excessive Z-axis expansion and perhaps poor copper ductility.
Example 16
This is an optical image of a micro-sectioned PWB using dark field imaging. The reflections of groups of glass fibers intersecting with the hole is an indication of laminate damage due to drilling, which can reduce CAF resistance.
Example 17
This is an example of a copper plating nodule on the ID of a PTH.
Example 18
This image shows delamination of epoxy resin from fiber bundles as well as resin starvation. It is likely that the resin starvation condition caused excessive moisture entrapment and subsequent popcorn damage when the moisture vaporized at elevated temperature (e.g. lamination or solder reflow).
Mike Rohlik says:
I always enjoy seeing the results of your testing and analysis. Experience is a great teacher. Better to learn from the wide, wide range of industry problems. We’ve been in the same boat searching for mysterious problems which became much clear when detailed analysis was performed. Though many would prefer to jump to conclusions without data … data wins. Everything else is just guessing.